Methods and apparatus for extracting integer remainders

ABSTRACT

Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extracts a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent scaling value. The residuary subset bitfield value is part of a range of contiguous bits that is associated with upper and lower boundary bit-position values that are part of the compound exponent scaling value. The methods and apparatus determine the remainder value based on the residuary subset bitfield value.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to processor systems and, moreparticularly, to methods and apparatus for extracting integer remainderswithin processor systems.

BACKGROUND

Many developments in connection with processor systems and,particularly, in connection with optimizing compilers, have beendirected to increasing the speed or efficiency of processorcomputational operations. Faster or more efficient processorcomputational operations can result in faster program execution times,particularly if the fundamental procedures or computational operationsthat are the building blocks of an overall program can be made faster ormore efficient. For example, the process of finding a quotient andremainder value associated with a division operation is a well-knownfundamental procedure or computational operation.

In general, the process of performing a division operation andcalculating a related remainder value is relatively more computationallyintensive and expensive in terms of processor usage than more basicarithmetic operations such as addition and multiplication. However, manyefficient techniques for calculating a quotient and a remainder are inwidespread use. For example, for a divisor that is known at compile timeand that is runtime invariant, it is possible to more efficiently orquickly calculate quotient values associated with runtime variantdividends using multiplication operations involving a value associatedwith a reciprocal of the runtime invariant divisor.

A processor system may determine a remainder value of interest by firstperforming a division operation. Often, a remainder value is of greaterinterest than a quotient. For example, when a processor system executesa modulus instruction, only a remainder value associated with a divisorvalue and a dividend value is returned.

One known technique for calculating a remainder is based on knowing thedivisor value at compile time and that the divisor value is runtimeinvariant. Because the divisor value is known at compile time, a scaledapproximate reciprocal of the divisor value can be calculated andpre-stored (i.e., prior to runtime), thereby enabling a processor systemto calculate, during runtime, a quotient and remainder using amultiplication of the dividend and the scaled approximate reciprocal ofthe divisor value. In particular, a quotient may be calculated atruntime by augmenting the multiplication with a bit shift or bitextraction to compensate for the scaling of the reciprocal value. Theremainder value can then be calculated by subtracting the product of thedivisor and the quotient from the dividend.

Although the above-described quotient and remainder calculationtechnique is relatively efficient in many instances, it treats allcombinations of dividend and divisor values in the same manner and doesnot consider more efficient solutions for specific dividend and divisorvalue combinations. Thus, traditional methods of computing quotient andremainder values within processor systems typically require the sameamount of computational work or processor usage, regardless of whether aless computationally intensive technique may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram illustrating a known multiplication-basedmethod for determining a quotient and remainder using a runtimeinvariant scaled approximate reciprocal of a divisor.

FIG. 2 is a flow diagram illustrating an example method for determiningan integer remainder.

FIG. 3 depicts an example of a residuary subset bitfield that may beused with the example method of FIG. 2 to determine a remainder value.

FIGS. 4-6 depict a more detailed flow diagram of example methods inwhich a remainder value may be determined using the method of FIG. 2.

FIG. 7 is a block diagram of an example hardware architecture that maybe configured to determine a remainder value using the methods of FIGS.2 and 4-6.

FIG. 8 is a block diagram of an example processor system that may beused to implement the apparatus and methods described herein.

DETAILED DESCRIPTION

FIG. 1 is a flow diagram illustrating a known multiplication-basedmethod for determining a quotient and remainder using a runtimeinvariant scaled approximate reciprocal of a divisor. As shown in FIG.1, during a compilation phase (block 120) a scaled approximatereciprocal of a divisor is calculated (block 122) and stored in a memory(block 125) for subsequent use during a runtime phase (block 130). Ascaled approximate reciprocal of a divisor may be calculated accordingto Equation 1 below. $\begin{matrix}{w \approx \frac{2^{p}}{m}} & {{Equation}\quad 1}\end{matrix}$

In Equation 1 above, the value m is a divisor value determined at thecompilation phase (block 120) and, thus, the value m is known in advanceof runtime. The value p is a scaling value chosen so that the value w(i.e., the scaled approximate reciprocal) is an integer value. Thedivisor value m is invariant during the runtime phase (block 130) and,as a result, the scaled approximate reciprocal value w can be calculatedonce during the compilation phase (block 120) and used multiple timesduring the runtime phase (block 130) to calculate quotient and/orremainder values for runtime variant dividend values, as described ingreater detail in connection with blocks 132 through 150 below.

During the runtime phase (block 130), the scaled approximate reciprocalvalue w can be used to calculate a product value q′ for a runtimevariant dividend value x (block 132) according to Equation 2 below.q′=w·x   Equation 2The value x is associated with a dividend having a value that may varyduring the runtime phase (block 130). The product value q′, whichrepresents a scaled approximate quotient value, is calculated during theruntime phase (block 130) by multiplying the scaled approximatereciprocal value w, which is a runtime invariant value, and the dividendvalue x, which may vary during the runtime phase (block 130).

The scaled approximate quotient value q′ contains a quotient value thatis associated with the scaling value p. In particular, a quotient valuecan be determined (block 140) during the runtime phase (block 130) usingthe scaled approximate quotient value q′ and the scaling value p asdescribed in Equation 3 below. $\begin{matrix}{q = \left\lfloor {q^{\prime} \cdot \frac{1}{2^{p}}} \right\rfloor} & {{Equation}\quad 3}\end{matrix}$As depicted in Equation 3 above, the quotient value q may be determined(block 140) by multiplying the scaled approximate quotient value q′ bythe inverse of two to the power of the value p. Alternatively, thequotient value q could be determined (block 140) by right bit-shiftingthe scaled approximate quotient value q′ a number of times equal to thevalue p.

The quotient value q, the divisor value m and the dividend value x maybe used during the runtime phase (block 130) to calculate the remaindervalue r (block 150) as shown in Equation 4 below.r=x−m·q   Equation 4As shown in Equation 4, the remainder value r may be determined (block150) by subtracting the product of the divisor value m, which is runtimeinvariant, and the quotient value q from the runtime variant dividendvalue x.

FIG. 2 is a flow diagram illustrating an example method for determiningan integer remainder. The example method of FIG. 2 is valid fornon-negative integer values. As shown in FIG. 2, during a compilationphase (block 220), a compensated scaled approximate reciprocal valuew_(c) of a divisor value m is calculated using a compound exponent(block 222) and is stored in a memory (block 225) for subsequent useduring a runtime phase (block 230). The compensated scaled approximatereciprocal value w_(c) of a divisor value m may be calculated as shownin Equation 5 below. ${w_{c} \approx w^{\prime}} = \frac{2^{s + k}}{m}$The value w′ is a scaled reciprocal value of the runtime invariantdivisor value m and is determined during the compilation phase (block220). The sum of the values s and k is used as a compound exponentscaling value. In some implementations, this value may be selected sothat 2^(k-1)<m<2_(k) and so that s+k is less than or equal to themaximum possible bit length value during a runtime phase (i.e., s+k isless than or equal to a 32-bit value on a 32-bit processor system using32-bit operations).

In another more specific implementation, when provided a fixed divisorvalue m and selecting a value of k as indicated above, a value of s maybe determined based on instruction implementations. One such exampleinvolves an operation ‘r=x modulo 3’ for producing a positive integerand a maximized range for the dividend value x. Implementing thisapproach using a processor from the Intel® Itanium™ family may becarried out using a “pmpyshr” instruction that performs a 16-bitmultiplication operation and a bit shift right operation. When usingthis instruction, the operation ‘r=x modulo 3’ results in a remaindervalue stored in the lower or least significant bit positions. Thisinstruction is limited to bit shifting 0, 7, 15 and 16 bits, thuslimiting the selection of a value of s to these numbers. In particular,for illustrative purposes, the values m and k may be selected to be m=3and k=2. Subsequently, according to Equation 5 above and Equation 6below, the selection of a value of s may determine a value of acompensation value a so that the overall range of the dividend value xis defined by $x < {\frac{2^{s}}{a}.}$Thus, when using the values m=3 and k=2 and Equations 5 and 6 it isreadily apparent that the range of the dividend value x is maximized toa value of 32,767 (i.e., 2¹⁵) when s is selected to be 15 or 16.Furthermore, because the “pmpyshr” instruction is capable of performingmultiplications having no more than 16 bits, the value w_(c), as shownin Equation 6 below, must be represented using a 16-bit value (i.e.,≦65,535 or ≦2¹⁶). Therefore, in this instance, s=15 is the best choice.However, in still other implementations, the compound exponent scalingvalue may be selected in other manners to suit the particularimplementation

The scaled reciprocal value w′, which may not be an integer value, is anintermediate value of the compensated scaled approximate reciprocalvalue w_(c). During the compilation phase (block 220), calculating thecompensated scaled approximate reciprocal value w_(c) of the runtimeinvariant divisor value m (block 222) involves performing a round-upoperation on the scaled reciprocal value w′. The round-up operationresults in an approximation value of w′, which is the compensated scaledapproximate reciprocal value w_(c) shown in Equation 5 above. Ininstances where the scaled reciprocal value W′ is a non-integer value,the scaled reciprocal value w′ is rounded up to the next nearest integervalue to yield the compensated scaled approximate reciprocal valuew_(c). On the other hand, in instances where the scaled reciprocal w′ isan integer value, it may be apparent that the runtime invariant divisorvalue m is a power of 2, therefore, a remainder value may be determinedto equal a bitfield value such as, for example, the residuary subsetbitfield value b as described in greater detail in connection with FIG.3.

The round-up operation performed on the scaled reciprocal value w′results in a compensation value a, which may be associated with an errorvalue or an approximation value. As shown below in Equation 6, thecompensation value a may be determined using the values w_(c), m and thecompound exponent values s and k. The compensated scaled approximatereciprocal value w_(c) may then be represented as shown in Equation 7.$\begin{matrix}{a = {{{w_{c} \cdot m} - {2^{s + k}\quad{where}\quad a}} > 0}} & {{Equation}\quad 6} \\{w_{c} = \frac{2^{s + k} + a}{m}} & {{Equation}\quad 7}\end{matrix}$The divisor value m is runtime invariant and, thus, the compensatedscaled approximate reciprocal value w_(c) of the divisor value m and thecompensation value a can be calculated once during the compilation phase(block 220). During the compilation phase (block 220), the values m,w_(c), s, k and a can be stored in a memory (block 225) and may be usedmultiple times during the runtime phase (block 230) to calculatequotient and/or remainder values for runtime variant dividend values, asdescribed in greater detail in connection with blocks 232 through 250below.

During the runtime phase (block 230), a product value associated with acompensated scaled approximate quotient value u may be determined for agiven dividend value x. The compensated scaled approximate quotientvalue u may be represented as a binary value and may be found via amultiplication operation as depicted in Equation 8 below.u=w _(c) ·x   Equation 8The multiplication of the compensated scaled approximate reciprocalvalue w_(c) and the runtime variant dividend value x result in acompensated scaled approximate quotient value u (block 232).

The compensated scaled approximate quotient value u is associated with acompound exponent scaling value s+k. In addition, the compensated scaledapproximate quotient value u includes a portion associated with aquotient q and a portion associated with a remainder r. Morespecifically, the compensated scaled approximate quotient value u iscomposed of a set of contiguous bits that includes a subset ofcontiguous bits that forms a residuary subset bitfield value b, which isassociated with an intermediate remainder calculating value that may beused to determine the remainder value r. The subset of contiguous bitsthat forms the residuary subset bitfield value b is within a range ofbit positions associated with the compound exponent scaling values s andk as set forth in Equation 9 below.b=(w _(c) ·x)_([s,s+k−1])  Equation 9During the runtime phase (block 230), the residuary subset bitfieldvalue b is extracted from the compensated scaled approximate quotientvalue u (block 240). In particular, the subset of contiguous bitsdefined by the inclusive bit position boundary values s and s+k−1 isextracted from the compensated scaled approximate quotient value u. Theextracted residuary subset bitfield value b may then be used during theruntime phase (block 230) to determine a remainder value (block 250) fora runtime invariant divisor value m and a runtime variant dividend valuex.

FIG. 3 depicts an example of a binary value 300 that may be used withthe example method of FIG. 2 to determine a remainder value. The set ofcontiguous bits that forms the binary value 300 may correspond to thecompensated scaled approximate quotient value u and may be divided intoat least two subsets of contiguous bits. A first subset of contiguousbits 310 is associated with a quotient value q and a second subset ofcontiguous bits 320 is associated with a residuary subset bitfield valueb, which may be used to determine a remainder value r as describedherein. The second subset of contiguous bits 320 that makes up theresiduary subset bitfield value b is defined to start at an inclusiveboundary bit position value s and has a bit length value k as set forthin Equation 9 above.

FIGS. 4-6 depict a more detailed flow diagram of example methods bywhich a remainder value may be determined using the method of FIG. 2. Ingeneral, the example methods shown in FIGS. 4-6 may enable aprocessor-based system to determine the remainder value r in differentmanners based on the divisor value m and the runtime values associatedwith the dividend x, the compensation value a, and the extractedresiduary subset bitfield value b. More specifically, as described ingreater detail in connection with FIGS. 4-6 below, the divisor value m,the compensation value a, and the residuary subset bitfield value b arecompared to threshold values associated with the compound exponentvalues s and k. The remainder value r is then determined or calculatedusing at least a portion of the extracted residuary subset bitfeld valueb and based on the result of one or more of the comparisons. In thismanner, a processor system (e.g., the processor system shown in FIG. 8)or a system based on an alternative architecture (e.g., the system shownin FIG. 7) may implement the methods as a plurality of test conditionsor comparisons that are executed in a sequence that enable the remaindervalue r to be determined in an efficient manner.

Now turning to FIG. 4, a flow diagram illustrating an example method fordetermining if the existence of a non-zero remainder value is provided.In general, the example method of FIG. 4 uses one or more of three testconditions or comparisons to determine whether or not the remaindervalue r equals zero.

In particular, a first test condition compares the divisor value m tothe value of two to the power of the residuary subset bitfield bitlength value k (block 410). In instances where the value of the divisorvalue m is less than or equal to the value 2^(k), a second testcondition compares the product of the compensation value a and thedividend value x to the value 2^(s) multiplied by the divisor value m(block 420). In cases where the product a·x is less than the product2^(s)·m, a zero test of the residuary subset bitfield value b isperformed (block 430). If the residuary subset bitfield value b is equalto zero at block 430, the remainder r is set equal to zero (block 450).

If any of the test conditions or comparisons carried out at blocks 410,420 or 430 are not satisfied (e.g., m>2^(k), a·x≧2^(s)·m or b≠0), theremainder value r is not set equal to zero and control is passed toblock 440 where an evaluation is made whether to determine an exactremainder value r. In instances where an exact remainder value r is notrelevant (block 440), then the process of FIG. 4 determines that theremainder value r is non-zero. On the other hand, in instances where theremainder value r is relevant (block 440), an exact remainder value rmay need to be determined and control is passed to the example methodshown in FIG. 5.

FIG. 5 is a flow diagram of an example method for determining aremainder value. More specifically, the example method of FIG. 5determines whether the remainder value r is equal to the residuarysubset bitfield value b. In general, the example method of FIG. 5 usesone or more of two test conditions or comparisons to determine whetheror not the remainder value r is equal to the residuary subset bitfieldvalue b.

In particular, the first test condition compares the divisor value m tothe value 2^(k)32 1 (block 530), where the value k is equal to theresiduary subset bitfield length. In instances where the divisor value mis equal to 2^(k)−1, a second test condition compares the product of thecompensation value a and the dividend value x to the value 2^(s) (block540), where the value s is equal to the residuary subset bitfieldinclusive boundary bit position. If the product a·x is less than thevalue 2^(s), the remainder value r is exactly equal to the residuarysubset bitfield value b (block 550).

On the other hand, if either of the test conditions or comparisonscarried out at blocks 530 or 540 is not satisfied (e.g., m≠2^(k)−1 ora·x≧2^(s)), the remainder value r is not set equal to the residuarybitfield value b and control is passed to the example methods shown inFIG. 6.

FIG. 6 is a flow diagram of three example methods for determining aremainder value. In general, each of the three example methods of FIG. 6uses one or more test conditions or comparisons to determine theremainder value.

As shown in FIG. 6, the first example method for determining a remaindervalue uses one or more of four test conditions or comparisons todetermine the remainder value. In particular, a first test conditioncompares the divisor value m to the value of two to the power of theresiduary subset bitfield bit length value k (block 620). In instanceswhere the value of the divisor value m is less than or equal to thevalue 2^(k), a second test condition determines if the divisor value mis divisible by two to the power of a value e (block 625), where e ischosen to be an integer value. In instances where the divisor value m isdivisible by the value 2^(e), a third test compares the product of thecompensation value a and the dividend value x to the value 2^(s+e)(block 630). For cases where the product a·x is less than the value2^(s+e), the relationship of the residuary subset bitfield value b andthe remainder value r may be represented by Equation 10 below. Thebrackets ‘└ . . . ┘’ denote the ‘floor’ function, so that └x┘ is aunique integer so that └x┘≦x<└x┘+1. $\begin{matrix}{b = \left\lfloor \frac{2^{k} \cdot r}{m} \right\rfloor} & {{Equation}\quad 10}\end{matrix}$As depicted in Equation 10, the residuary subset bitfield value b isequal to the floor function of two to the power of the residuary subsetbitfield bit length value k multiplied by the remainder value r anddivided by the divisor value m.

Furthermore, for cases where the product a·x is less than the value2^(s+e), a zero test of the residuary subset bitfield value b isperformed (block 635). If the residuary subset bitfield value b is equalto zero at block 635, the remainder value r is set equal to zero (block640). However, if the residuary subset bitfield value b is not equal tozero, the remainder value r may be determined via the combination of anaddition operation, a short multiplication operation and a shiftoperation (block 660) according to Equation 11 below. $\begin{matrix}{r = \left\lfloor \frac{m \cdot \left( {b + 1} \right)}{2^{k}} \right\rfloor} & {{Equation}\quad 11}\end{matrix}$As shown in Equation 11, the remainder value r may be determined by thefloor function of the divisor value m multiplied by the quantity of theresiduary subset bitfield value b plus one and right bit-shifting theresulting product a number of times equal to the residuary subsetbitfield length value k.

If any one of the test conditions or comparisons carried out at blocks620, 625 or 630 is not satisfied (e.g., m>2^(k), m not divisible by2^(e) or a·x≧2^(s+e)), control is passed to the blocks of a secondexample method for determining a remainder value.

A second example method for determining a remainder value, as shown inFIG. 6, uses one or more of two test conditions or comparisons todetermine the remainder value. In particular, a first test conditioncompares the product of a compensation value a and a dividend value x tothe value 2^(s)(2^(k)-m) (block 650). In instances where the product a·xis less than the value 2^(s)(2^(k)-m), the size of the divisor value mmay be analyzed to determine whether the remainder value r may bedetermined via a look-up table (block 655). A look-up table may be usedfor determining the remainder value r if the size of the divisor value mis deemed to be ‘relatively small’. For instance, in a processor systemhaving limited memory, the divisor value m equal to ten (i.e. m=10) maybe ‘relatively small’ enough to implement since a look-up table wouldinclude at most sixteen entries and would require minimal memory. On theother hand, it may not be suitable to implement a look-up table on aprocessor system having limited memory if the divisor value m is not‘relatively small’, thereby requiring a larger number of entries suchas, for example, 1,048,576 entries (i.e. m=100,000). However, ininstances where a processor system includes a large memory capable ofhandling large amounts of data such as, for example, large look-uptables, it may be possible to implement a look-up table for the exampleof the divisor value m equal to 100,000 to determine the remainder valuer. In any case, if the divisor value m is deemed ‘relatively small’ inview of the processor system and available memory, the remainder value rmay be determined via a look-up table retrieval technique (block 680). Alook-up table retrieval technique may be implemented with multiple tableentry reference locations associated with the residuary subset bitfieldb. Furthermore, each look-up table entry may include a remainder valuethat is associated with a respective table entry reference location.However, if the divisor value m is deemed not ‘relatively small’ in viewof the processor system and available memory, the remainder value r maybe determined via a combination of an addition operation, a shortmultiplication operation and a right bit-shift operation (block 660)according to Equation 11 above. Furthermore, if the test conditioncomparison carried out by block 650 is not satisfied (i.e.,a·x≧2^(s)(2^(k)-m)), control is passed to the blocks of a third examplemethod for determining a remainder value.

A third example method for determining a remainder value shown in FIG. 6uses at least one test condition or comparison to determine theremainder value. In particular, a first test condition compares theproduct of a compensation value a and the dividend value x to the value2^(s)((2^(k)+1)−m) (block 670). In instances where the product a·x isless than 2^(s)((2^(k)+1)−m), the relationship of the residuary subsetbitfield value b and the remainder value r may be represented byEquation 12 below and the remainder value r may be determined via alook-up table retrieval technique (block 680). $\begin{matrix}{\left\lfloor \frac{2^{k} \cdot r}{m} \right\rfloor \leq b < \left\lfloor \frac{2^{k} \cdot \left( {r + 1} \right)}{m} \right\rfloor} & {{Equation}\quad 12}\end{matrix}$As depicted by Equation 12, the floor function of the remainder value rmultiplied by the value 2^(k) and divided by the divisor value m is lessthan or equal to the residuary subset bitfield value b. Also, theresiduary subset bitfield value b is less than the product of theremainder value r plus one and 2^(k) divided by the divisor value m.

If the test condition comparison carried out at block 670 is notsatisfied (e.g., a·x≧2^(s)((2^(k)+1)−m)), the remainder value r may bedetermined via traditional methods for determining a remainder (block690). For example, one traditional method for determining the remaindervalue r involves recovering a quotient value q from a compensated scaledapproximate quotient value u according to Equation 13 below. Using thequotient value q, the dividend value x and the divisor value m, theremainder value r may then be determined using a combination of amultiplication operation and a subtraction operation as shown inEquation 14 below. $\begin{matrix}{q = {u \cdot \frac{1}{2^{s + k}}}} & {{Equation}\quad 13} \\{r = {{x - {{m \cdot q}\quad{where}\quad 0}} \leq r < m}} & {{Equation}\quad 14}\end{matrix}$As depicted in Equation 13, the quotient value q is equal to thecompensated scaled approximate quotient value u right bit-shifted anumber of times equal to the compound exponent value s+k. Furthermore,as shown in Equation 14, the remainder value r is equal to the dividendvalue x minus the product of the divisor value m and the quotient valueq.

FIG. 7 is a block diagram of an example hardware architecture 700 thatmay be configured to determine a remainder value using the methods ofFIGS. 2 and 4-6. As shown in FIG. 7, the example hardware architecture700 includes a compensated scaled approximate reciprocal generator 710,a multiplier 720, a bit extractor 730, a parameter value comparator 740and a remainder value generator 750.

The example hardware architecture or system 700 shown in FIG. 7 may beconfigured to generate a compensated scaled approximate reciprocal valuew_(c) of a divisor value m and a dividend value x, a compensated scaledapproximate quotient value u associated with quotient and remaindervalues of the divisor value m, and dividend value x in accordance withthe methods depicted in FIGS. 2 and 4-6. More specifically, the examplesystem 700 may implement these methods as a plurality of test conditionsor comparisons that are executed in a sequence to determine theremainder value r in the most efficient manner.

The compensated scaled approximate reciprocal generator 710 enables theexample system 700 to generate a compensated scaled approximatereciprocal w_(c) of a divisor value m. The compensated scaledapproximate reciprocal w_(c) may be generated according to Equations 5,6 and 7 as shown above using a divisor value m, a compensation value aand compound exponent values s and k, where s is equal to a residuarysubset bitfield inclusive boundary bit position and k is equal to aresiduary subset bitfield bit length.

The multiplier 720 enables the example system 700 to generate acompensated scaled approximate quotient value u, which is a product ofthe compensated scaled approximate reciprocal w_(c) and a dividend valuex according to Equation 8. The compensated scaled approximate quotientvalue u includes a quotient value of the divisor value m and thedividend value x. Furthermore, the compensated scaled approximatequotient value u includes a residuary subset bitfield value b that isassociated with a remainder value r of the divisor value m and thedividend value x.

The bit extractor 730 enables the system architecture 700 to extract aresiduary subset bitfield value b from the compensated scaledapproximate quotient value u. The range of contiguous bits that formsthe residuary subset bitfield value b is associated with the compoundexponent values s and k according to Equation 9 above, where s is equalto a residuary subset bitfield inclusive boundary bit position and k isequal to a residuary subset bitfield bit length.

The parameter value comparator 740 enables the example system 700 todetermine the most efficient method, based on the methods fordetermining a remainder value of FIGS. 4-6, by which to generate aremainder value. In particular, the parameter value comparator 740determines the method by which to generate a remainder value r based ona divisor value m, a dividend value x, the compensation value a, and theresiduary subset bitfield value b. More specifically, as described ingreater detail in connection with FIGS. 4-6, the parameter valuecomparator (block 740) may compare values of the divisor value m, thecompensation value a, and the residuary subset bitfield value b tovalues associated with the compound exponent values s and k. Theremainder value r may then be generated using at least a portion of theresiduary subset bitfield value b and based on the result of one or moreof the comparisons.

The remainder value generator 750 enables the example system 700 togenerate a remainder value r using the remainder generation methodindicated by the parameter value comparator 740. Thus, the remaindervalue r may be generated in any one of the several manners depicted inFIGS. 4-6.

FIG. 8 is a block diagram of an example processor system 810 that may beused to implement the apparatus and methods described herein. As shownin FIG. 8, the processor system 810 includes a processor 812 that iscoupled to an interconnection bus or network 814. The processor 812includes a register set or register space 816, which is depicted in FIG.8 as being entirely on-chip, but which could alternatively be locatedentirely or partially off-chip and directly coupled to the processor 812via dedicated electrical connections and/or via the interconnectionnetwork or bus 814. The processor 812 may be any suitable processor,processing unit or microprocessor such as, for example, a processor fromthe Intel X-Scale™ family, the Intel Pentium™ family, etc. In theexample described in detail below, the processor 812 is a thirty-two bitIntel processor, which is commonly referred to as an IA-32 processor.Although not shown in FIG. 8, the system 810 may be a multi-processorsystem and, thus, may include one or more additional processors that areidentical or similar to the processor 812 and which are coupled to theinterconnection bus or network 814.

The processor 812 of FIG. 8 is coupled to a chipset 818, which includesa memory controller 820 and an input/output (I/O) controller 822. As iswell known, a chipset typically provides I/O and memory managementfunctions as well as a plurality of general purpose and/or specialpurpose registers, timers, etc. that are accessible or used by one ormore processors coupled to the chipset. The memory controller 820performs functions that enable the processor 812 (or processors if thereare multiple processors) to access a system memory 824, which mayinclude any desired type of volatile memory such as, for example, staticrandom access memory (SRAM), dynamic random access memory (DRAM), etc.The I/O controller 822 performs functions that enable the processor 812to communicate with peripheral input/output (I/O) devices 826 and 828via an I/O bus 830. The I/O devices 826 and 828 may be any desired typeof I/O device such as, for example, a keyboard, a video display ormonitor, a mouse, etc. While the memory controller 820 and the I/Ocontroller 822 are depicted in FIG. 8 as separate functional blockswithin the chipset 818, the functions performed by these blocks may beintegrated within a single semiconductor circuit or may be implementedusing two or more separate integrated circuits.

The methods described herein may be implemented using a primarilyhardware-based system (e.g., the system 700 shown in FIG. 7), aprimarily processor-based or software-based system (e.g., the system 800shown in FIG. 8), or another system employing any desired combination ofhardware and software. In the case of a primarily hardware-based systemsuch as that shown in FIG. 7, gate arrays, application specificintegrated circuits, discrete semiconductor components, etc. may be usedto perform the remainder generation techniques described herein. In thecase of a primarily processor-based system such as that shown in FIG. 8,software or instructions stored on a machine readable medium (e.g., arandom access memory, a magnetic storage medium, an optical storagemedium, etc.) may be executed by a processor (e.g., the processor 812)to perform the methods described herein. Of course, any desiredcombination of hardware and software may be employed to accomplish thesame or similar results.

In addition, while the methods depicted in FIGS. 4-6 are described asincluding a plurality of runtime test conditions for selecting anappropriate, efficient remainder generation or determination techniqueduring runtime, one or more of these conditions could be eliminated fromruntime operation. For example, because the value of the divisor m isknown during compile time and is runtime invariant, the tests orcomparisons depicted in blocks 410, 530 and 620 could be performedduring compile time, thereby reducing the number of remainderdetermination techniques needed during runtime. In other words, fewerthan all the blocks shown in FIGS. 4-6 may be used during runtime todetermine remainder values as described herein. Further, the arrangementor sequence of the blocks may be changed, if desired, to accomplish thesame or similar results. Although certain methods, apparatus andarticles of manufacture have been described herein, the scope ofcoverage of this patent is not limited thereto. To the contrary, thispatent covers all methods, apparatuses and articles of manufacturefairly falling within the scope of the appended claims, either literallyor under the doctrine of equivalents.

1. A method comprising: multiplying a dividend value by a first value togenerate a second value associated with a product, wherein the firstvalue is associated with a scaled approximate reciprocal of a divisorvalue, and wherein the scaled approximate reciprocal of the divisorvalue includes a compound exponent value; extracting a third value fromthe second value, wherein the third value is generated using at least asubset bitfield of the second value; and determining a remainder valuebased on the third value.
 2. A method as defined in claim 1, wherein thedividend value and the divisor value are non-negative integers.
 3. Amethod as defined in claim 1, wherein determining the remainder valueincludes calculating a scaling value by raising two to the power of thecompound exponent value.
 4. A method as defined in claim 3, whereindetermining the remainder value includes calculating a fourth value byadding the scaling value to a compensation value associated with arounding-up process.
 5. A method as defined in claim 4, whereindetermining the remainder value includes calculating the first value bydividing the fourth value by the divisor value.
 6. A method as definedin claim 1, wherein the second value is stored in a range of contiguousbits.
 7. A method as defined in claim 6, wherein the range of contiguousbits includes a residuary subset of contiguous bits, and wherein theresiduary subset of contiguous bits includes the third value.
 8. Amethod as defined in claim 1, wherein determining the remainder valueincludes setting the remainder value equal to the third value.
 9. Amethod as defined in claim 1, wherein determining the remainder valueincludes setting the remainder value equal to zero if the third valueequals zero.
 10. A method as defined in claim 1, wherein determining theremainder value includes determining that the dividend value is exactlydivisible by the divisor value if the third value equals zero.
 11. Amethod as defined in claim 1, wherein determining the remainder valueincludes locating the remainder value stored within a data structurelocation associated with the third value.
 12. A method as defined inclaim 1, wherein determining the remainder value includes calculatingthe remainder value by adding, multiplying and bit-shifting, whereinadding results in a sum associated with the third value and one, whereinmultiplying produces a product of the divisor value and the sum, andwherein bit-shifting includes right bit-shifting the product of thedivisor value and the sum.
 13. An apparatus comprising: a processorsystem including a memory; instructions stored in the memory that enablethe processor system to: multiply a dividend value by a first value togenerate a second value associated with a product, wherein the firstvalue is associated with a scaled approximate reciprocal of a divisorvalue, and wherein the scaled approximate reciprocal of the divisorvalue includes a compound exponent value; extract a third value from thesecond value, wherein the third value is generated using at least asubset bitfield of the second value; and determine a remainder valuebased on the third value.
 14. An apparatus as defined in claim 13,wherein the dividend value and the divisor value are non-negativeintegers.
 15. An apparatus as defined in claim 13, wherein theinstructions enable the processor system to calculate a scaling value byraising two to the power of the compound exponent value.
 16. Anapparatus as defined in claim 15, wherein the instructions enable theprocessor system to calculate a fourth value by adding the scaling valueto a compensation value associated with a round-up process.
 17. Anapparatus as defined in claim 16, wherein the instructions enable theprocessor system to calculate the first value by dividing the fourthvalue by the divisor value.
 18. An apparatus as defined in claim 13,wherein the second value is stored in a range of contiguous bits.
 19. Anapparatus as defined in claim 18, wherein the range of contiguous bitsincludes a residuary subset of contiguous bits, and wherein the thirdvalue is stored in the residuary subset of contiguous bits.
 20. Anapparatus as defined in claim 13, wherein the remainder value is equalto the third value.
 21. An apparatus as defined in claim 13, wherein theremainder value is equal to zero if the third value equals zero.
 22. Anapparatus as defined in claim 13, wherein the instructions enable theprocessor system to determine that the dividend value is exactlydivisible by the divisor value if the third value equals zero.
 23. Anapparatus as defined in claim 13, wherein the instructions enable theprocessor system to locate the remainder value stored within a datastructure location associated with the third value.
 24. An apparatus asdefined in claim 13, wherein the instructions enable the processorsystem to calculate the remainder value using an addition operation, amultiplication operation and a bit shift operation, wherein the additionoperation results in a sum associated with the third value and one,wherein the multiplication operation produces a product of the divisorvalue and the sum, and wherein the bit-shift operation includes rightbit-shifting the product of the divisor value and the sum.
 25. Acomputer readable medium having instructions stored thereon that, whenexecuted, cause a machine to: multiply a dividend value by a first valueto generate a second value associated with a product, wherein the firstvalue is associated with a scaled approximate reciprocal of a divisorvalue, and wherein the scaled approximate reciprocal of the divisorvalue includes a compound exponent value; extract a third value from thesecond value, wherein the third value is generated using at least asubset bitfield of the second value; and determine the remainder valuebased on the third value.
 26. A computer readable medium as defined inclaim 25, wherein the dividend value and the divisor value arenon-negative integers.
 27. A computer readable medium as defined inclaim 25 having instructions stored thereon that, when executed, causethe machine to calculate a scaling value by raising two to the power ofthe compound exponent value.
 28. A computer readable medium as definedin claim 27 having instructions stored thereon that, when executed,cause the machine to calculate a fourth value by adding the scalingvalue to a compensation value associated with a round-up process.
 29. Acomputer readable medium as defined in claim 27 having instructionsstored thereon that, when executed, cause the machine to calculate thefirst value by dividing the fourth value by the divisor value.
 30. Acomputer readable medium as defined in claim 25, wherein the secondvalue is stored in a range of contiguous bits.
 31. A computer readablemedium as defined in claim 30, wherein the range of contiguous bitsincludes a residuary subset of contiguous bits, and wherein the thirdvalue is stored in the residuary subset of contiguous bits.
 32. Acomputer readable medium as defined in claim 25, wherein the remaindervalue is equal to the third value.
 33. A computer readable medium asdefined in claim 25, wherein the remainder value is equal to zero if thethird value equals zero.
 34. A computer readable medium as defined inclaim 25 having instructions stored thereon that, when executed, causethe machine to determine that the dividend value is exactly divisible bythe divisor value if the third value equals zero.
 35. A computerreadable medium as defined in claim 25 having instructions storedthereon that, when executed, cause a machine to locate the remaindervalue stored within a data structure location associated with the thirdvalue.
 36. A computer readable medium as defined in claim 25 havinginstructions stored thereon that, when executed, cause the machine tocalculate the remainder value using an addition operation, amultiplication operation and a bit shift operation, wherein the additionoperation results in a sum associated with the third value and one,wherein the multiplication operation produces a product of the divisorvalue and the sum, and wherein the bit-shift operation includes rightbit-shifting the product of the divisor value and the sum.
 37. A methodcomprising: calculating a first value associated with a scaledapproximate reciprocal of a divisor value; calculating a second value,wherein the second value is a product of a dividend value and the firstvalue, and wherein the second value is stored in a first range ofcontiguous bits; extracting a third value from a second range ofcontiguous bits that lies within the first range of contiguous bits; andcomputing a remainder value based on the third value.
 38. A method asdefined in claim 37, wherein the first value is associated with acompound exponent value and a compensation value.
 39. A method asdefined in claim 38, wherein the compound exponent value is associatedwith upper and lower bit positions of the second range of contiguousbits.
 40. A method as defined in claim 38, wherein the compensationvalue is associated with a round-up process.
 41. A method as defined inclaim 37, wherein computing the remainder value includes calculating theremainder value by adding, multiplying and bit-shifting.
 42. A method asdefined in claim 37, wherein computing the remainder value includeslocating the remainder value in a data structure, and wherein the thirdvalue is associated with a location reference to an entry in the datastructure.
 43. A system comprising: a processor system including amemory; and instructions stored in the memory that enable the processorsystem to: calculate a first value associated with a scaled approximatereciprocal of a divisor value; calculate a second value, wherein thesecond value is a product of a dividend value and the first value, andwherein the second value is stored in a first range of contiguous bits;extract a third value from a second range of contiguous bits that lieswithin the first range of contiguous; and compute a remainder valuebased on the third value.
 44. A system as defined in claim 43, whereinthe first value is associated with a compound exponent value and acompensation value.
 45. A system as defined in claim 44, wherein thecompound exponent value is associated with upper and lower bit positionsof the second range of contiguous bits.
 46. A system as defined in claim44, wherein the compensation value is associated with a round-upprocess.
 47. A system as defined in claim 43, wherein the instructionsenable the processor system to calculate the remainder value using atleast one of an addition operation, a multiplication operation and abit-shift operation.
 48. A system as defined in claim 43, wherein theinstructions enable the processor system to locate the remainder valuein a data structure, wherein the third value is associated with alocation reference to an entry in the data structure.
 49. A computerreadable medium having instructions stored thereon that, when executed,cause a machine to: calculate a first value associated with a scaledapproximate reciprocal of a divisor value; calculate a second value,wherein the second value is a product of a dividend value and the firstvalue, and wherein the second value is stored in a first range ofcontiguous bits; extract a third value from a second range of contiguousbits that lies within the first range of contiguous bits includes; andcompute a remainder value based on the third value.
 50. A computerreadable medium as defined in claim 49, wherein the first value isassociated with a compound exponent value and a compensation value. 51.A computer readable medium as defined in claim 50, wherein the compoundexponent value is associated with upper and lower bit positions of thesecond range of contiguous bits.
 52. A computer readable medium asdefined in claim 50, wherein the compensation value is associated with around-up process.
 53. A computer readable medium as defined in claim 49having instructions stored thereon that, when executed, cause themachine to calculate the remainder value using at least one of anaddition operation, a multiplication operation and a bit-shiftoperation.
 54. A computer readable medium as defined in claim 49 havinginstructions stored thereon that, when executed, cause the machine tolocate the remainder value in a data structure, wherein the third valueis associated with a location reference to an entry in the datastructure.
 55. A method for computing a remainder value comprising:extracting a first range of contiguous bits from a second range ofcontiguous bits, wherein the first range of contiguous bits is bound byan upper-limit bit position value and a lower-limit bit position value,and wherein the first range of contiguous bits is associated with anintermediate remainder calculating value; and computing the remaindervalue based on the intermediate remainder calculating value.
 56. Amethod as defined in claim 55, wherein computing the remainder valueincludes calculating the remainder value by adding, multiplying andbit-shifting, wherein adding results in a sum associated with theintermediate remainder calculating value and one, wherein multiplyingproduces a product of a dividend value and the sum, and whereinbit-shifting consists of right bit-shifting the product of a dividendvalue and the sum.
 57. A method as defined in claim 55, whereincomputing the remainder value includes setting the remainder value equalto zero if the intermediate remainder calculating value equals zero. 58.A method as defined in claim 55, wherein computing the remainder valueincludes determining that a dividend value is exactly divisible by adivisor value if the intermediate remainder calculating value equalszero.
 59. A method as defined in claim 55, wherein computing theremainder value includes locating the remainder value in a datastructure, wherein the intermediate remainder calculating value isassociated with a location reference to an entry in the data structure.60. A method as defined in claim 55, wherein computing the remaindervalue includes determining that the remainder value is equal to theintermediate remainder calculating value.
 61. A system comprising: aprocessor system including a memory; and instructions stored in thememory that enable the processor system to: extract a first range ofcontiguous bits from a second range of contiguous bits, wherein thefirst range of contiguous bits is bound by an upper-limit bit positionvalue and a lower-limit bit position value, and wherein the first rangeof contiguous bits is associated with an intermediate remaindercalculating value; and compute a remainder value based on theintermediate remainder calculating value.
 62. A system as defined inclaim 61, wherein the instructions enable the processor system tocalculate the remainder value using an addition operation, a shortmultiplication operation and a bit-shift operation, wherein the additionoperation results in a sum associated with the intermediate remaindercalculating value and one, wherein the short multiplication operationproduces a product of a dividend value and the sum, and wherein thebit-shift operation consists of right bit-shifting the product of adividend value and the sum.
 63. A system as defined in claim 61, whereinthe instructions enable the processor system to determine that theremainder value is equal to zero if the intermediate remaindercalculating value equals zero.
 64. A system as defined in claim 61,wherein the instructions enable the processor system to determine that adividend value is exactly divisible by a divisor value if theintermediate remainder calculating value equals zero.
 65. A system asdefined in claim 61, wherein the instructions enable the processorsystem to locate the remainder value in a data structure, wherein theintermediate remainder calculating value is associated with a locationreference to an entry in the data structure.
 66. A system as defined inclaim 61, wherein the instructions enable the processor system todetermine that the remainder value is equal to the intermediateremainder calculating value.
 67. A computer readable medium havinginstructions stored thereon that, when executed, cause a machine to:extract a first range of contiguous bits from a second range ofcontiguous bits, wherein the first range of contiguous bits is bound byan upper-limit bit position value and a lower-limit bit position value,and wherein the first range of contiguous bits is associated with anintermediate remainder calculating value; and compute the remaindervalue based on the intermediate remainder calculating value.
 68. Acomputer readable medium as defined in claim 67, having instructionsstored thereon that, when executed, cause the machine to calculate theremainder value using an addition operation, a short multiplicationoperation and a bit-shift operation, wherein the addition operationresults in a sum associated with the intermediate remainder calculatingvalue and one, wherein the short multiplication operation produces aproduct of a dividend value and the sum, and wherein the bit-shiftoperation consists of right bit-shifting the product of a dividend valueand the sum.
 69. A computer readable medium as defined in claim 67,having instructions stored thereon that, when executed, cause themachine to determine that the remainder value is equal to zero if theintermediate remainder calculating value equals zero.
 70. A computerreadable medium as defined in claim 67, having instructions storedthereon that, when executed, cause the machine to determine that adividend value is exactly divisible by a divisor value if theintermediate remainder calculating value equals zero.
 71. A computerreadable medium as defined in claim 67, having instructions storedthereon that, when executed, cause the machine to locate the remaindervalue in a data structure, wherein the intermediate remaindercalculating value is associated with a location reference to an entry inthe data structure.
 72. A computer readable medium as defined in claim67, having instructions stored thereon that, when executed, cause themachine to determine that the remainder value is equal to theintermediate remainder calculating value.
 73. A system comprising: a bitextractor; and a remainder value generator coupled to the bit extractor,wherein the bit extractor is configured to extract a residuary subsetbitfield associated with an intermediate remainder calculating value anda compound exponent value, and wherein the remainder value generator isconfigured to generate a remainder value that is associated with theintermediate remainder calculating value.
 74. A system as defined inclaim 73, wherein the residuary subset bitfield is associated with anupper-boundary bit position value and a lower-boundary bit positionvalue, and wherein the compound exponent value includes theupper-boundary bit position value and the lower-boundary bit positionvalue.
 75. A system as defined in claim 73, wherein the remainder valuegenerator is configured to generate the remainder value using at leastone of an addition operation, a multiplication operation and a bit-shiftoperation.
 76. A system as defined in claim 73, wherein the remaindervalue generator is configured to generate a remainder value equal tozero if the intermediate remainder calculating value equals zero.
 77. Asystem as defined in claim 73, wherein the remainder value generator isconfigured to locate the remainder value stored within a data structurelocation associated with the intermediate remainder calculating value.